FABulous.geometry_generator.tile_geometry ========================================= .. py:module:: FABulous.geometry_generator.tile_geometry .. autoapi-nested-parse:: Tile geometry generation and management for FABulous FPGA tiles. This module provides the `TileGeometry` class for representing and generating the geometric layout of FPGA tiles, including switch matrices, BELs, and interconnect wires. It handles both direct connections to neighboring tiles and complex stair-like routing for longer-distance connections. Classes ------- .. py:class:: TileGeometry() A data structure representing the geometry of a tile. Initializes all attributes to default values: empty name, zero dimensions, no border, and empty lists for geometric components. .. attribute:: name Name of the tile :type: str .. attribute:: width Width of the tile :type: int .. attribute:: height Height of the tile :type: int .. attribute:: border Border of the fabric the tile is on :type: Border .. attribute:: smGeometry Geometry of the tiles switch matrix :type: SmGeometry .. attribute:: belGeomList List of the geometries of the tiles bels :type: list[BelGeometry] .. attribute:: wireGeomList List of the geometries of the tiles wires :type: list[WireGeometry] .. attribute:: stairWiresList List of the stair-like wires of the tile :type: list[StairWires] .. attribute:: currPortGroupId Current port group ID being processed :type: int .. attribute:: queuedAdjustmentBottom Queued adjustment for bottom positioning :type: int .. attribute:: queuedAdjustmentLeft Queued adjustment for left positioning :type: int .. attribute:: reserveStairSpaceBottom Whether to reserve space at bottom for stair wires :type: bool .. attribute:: reserveStairSpaceLeft Whether to reserve space at left for stair wires :type: bool .. attribute:: eastMiddleY Middle Y coordinate for east side :type: int .. attribute:: northMiddleX Middle X coordinate for north side :type: int .. attribute:: southMiddleX Middle X coordinate for south side :type: int .. attribute:: westMiddleY Middle Y coordinate for west side :type: int **Methods:** .. py:method:: adjustDimensions(maxWidthInColumn, maxHeightInRow, maxSmWidthInColumn, maxSmRelXInColumn) Adjust tile dimensions to match maximum values in fabric grid. Normalizes the tile dimensions and switch matrix positioning to align with the maximum dimensions found in the same fabric column/row, ensuring uniform tile sizing across the fabric. :param maxWidthInColumn: Maximum width among tiles in the same column :type maxWidthInColumn: int :param maxHeightInRow: Maximum height among tiles in the same row :type maxHeightInRow: int :param maxSmWidthInColumn: Maximum switch matrix width in the same column :type maxSmWidthInColumn: int :param maxSmRelXInColumn: Maximum switch matrix relative X position in the same column :type maxSmRelXInColumn: int .. py:method:: adjustSmPos(lowestSmYInRow, padding) Ajusts the position of the switch matrix. This is done by using the lowest Y coordinate of any switch matrix in the same row for reference. After this step is completed for all switch matrices, their southern edge will be on the same Y coordinate, allowing for easier inter-tile routing. .. py:method:: generateBelWires() Generate the wires between the switch matrix and its bels. .. py:method:: generateDirectWires(padding) Generate wires to neigbouring tiles. .. py:method:: generateGeometry(tile, padding) Generate the geometry for a tile. Creates geometric representations for all BELs and the switch matrix, then calculates the overall tile dimensions based on the generated components and padding requirements. :param tile: The `Tile` object to generate geometry for :type tile: Tile :param padding: The padding space to add around components :type padding: int .. py:method:: generateIndirectWires(padding) Generate wires to non-neighbouring tiles. These wires require staircase-like routing patterns to reach tiles that are not direct neighbors (offset >= 2). The routing varies by tile side and wire direction. :param padding: The padding space to add around wire routing :type padding: int :raises InvalidPortType: If a port has abs(offset) > 1 but no tile side assigned. .. py:method:: generateWires(padding) Generate all wire geometries for the tile. Creates wire geometries for BEL connections, direct connections to neighboring tiles, and indirect connections requiring stair-like routing. Ensures proper alignment of wire positions across different tile types. :param padding: The padding space to add around wire routing :type padding: int .. py:method:: indirectEastSideWire(portGeom, padding) Generate indirect wires on the east side of the tile with stair-like routing. Creates staircase-shaped wire routing for connections that span multiple tiles eastward. Manages stair wire generation and space reservation based on wire direction and grouping. :param portGeom: The port geometry defining the wire characteristics :type portGeom: PortGeometry :param padding: The padding space around the wire routing :type padding: int .. py:method:: indirectNorthSideWire(portGeom, padding) Generate indirect wires with stair-like routing. Creates staircase-shaped wire routing for connections that span multiple tiles northward. Manages stair wire generation and space reservation based on wire direction and grouping. :param portGeom: The port geometry defining the wire characteristics :type portGeom: PortGeometry :param padding: The padding space around the wire routing :type padding: int .. py:method:: indirectSouthSideWire(portGeom) Generate indirect wires on the south side without creating stair-like wires. Creates L-shaped wire routing for southward connections. Unlike north side wires, this method only generates the connection wires and reserves space for stair wires created by the north side method. :param portGeom: The port geometry defining the wire characteristics :type portGeom: PortGeometry .. py:method:: indirectWestSideWire(portGeom) Generate indirect wires on the west side without creating stair-like wires. Creates L-shaped wire routing for westward connections. Unlike east side wires, this method only generates the connection wires and reserves space for stair wires created by the east side method. :param portGeom: The port geometry defining the wire characteristics :type portGeom: PortGeometry .. py:method:: saveToCSV(writer) Save tile geometry data to CSV format. Writes the tile geometry information including dimensions and all geometric components (switch matrix, BELs, wires, stair wires) to a CSV file using the provided writer. :param writer: The CSV writer object to use for output :type writer: object .. py:method:: setBelPositions(padding) Set BEL positions.